MIPS

What is MIPS? MIPS ( Microprocessor without interlocked Pipeline Stages) is a reduced instruction set computer(RICS) instruction set (SET) developed by MIPS Technologies (formerly MIPS Computer Systems, Inc). The early MIPS architectures were 32-bit, with 64-bit versions added later. Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32( for 32-bit implementations) and MIPS64( for 64-bit implementations). MIPS32 and MIPS64 define a control set as well as the instruction set. MIPS R2000 Architecture MIPS have only a small number or ways that is computes addresses in memory. The addresses can be an address of an instruction (for branch and jump instructions) or it can be an address of data (for load & store instruction). INSTRUCTION FORMATS Instruction format is not an address mode. it is how an instruction is put together, whereas addressing mode is how the address of an operand is determined. There are three types of instruction format : Register Type ( R-Type ) Immediate Type ( I-Type ) Jump Type ( J-Type ) Register Type (R-type) R-type instructions refer to register type instructions. Of the three formats, the R-type is the most complex. This group contains all instructions that do not require an immediate value, target offset, memory address displacement, or memory address to specify an operand. All R-type instruction use opcode 000000. The prototypical R-type instruction is: add $rd, $rs, $rt where $rd refers to some register d (d is shown as a variable, however, to use the instruction, you must put a number between 0 and 31, inclusive for d). $rs, $rt are also registers. The semantics of the instruction are; R[d] = R[s] + R[t] where the addition is signed addition. You will notice that the order of the registers in the instruction is the destination register ($rd), followed by the two source registers ($rs and $rt). However, the actual binary format (shown in the table above) stores the two source registers first, then the destination register. Thus, how the assembly language programmer uses the instruction, and how the instruction is stored in binary, do not always have to match. Let's explain each of the fields of the R-type instruction. opcode (B31-26) : Opcode is short for "operation code". The opcode is a binary encoding for the instruction. Opcodes are seen in all ISAs. In MIPS, there is an opcode for add. The opcode in MIPS ISA is only 6 bits. Ordinarily, this means there are only 64 possible instructions. Even for        a RISC ISA, which typically has few instructions, 64 is quite small. For R-typeinstructions, an additional 6 bits are used (B5-0) called the function. Thus, the 6 bits of the opcode and the 6 bits of the function specify the kind of instruction for R-type instructions. rd (B25-21) : this is the destination register. The destination register is the register where the result of the operation is stored. rs (B20-16) : This is the first source register. The source register is the register that holds one of the arguments of the operation. rt (B15-11) : This is the second source register. shift amount (B10-6) : The amount of bits to shift. Used in shift instructions. function (B5-0) : An additional 6 bits used to specify the operation, in addition to the opcode. Immediate Type ( I-Type ) I-type is short for "immediate type". The format of an I-type instruction looks like:  This group includes instructions with an immediate operand, branch instructions and load and store instructions. All opcodes except 000000, 00001x, and 0110xx and 0100xx are used for I-type instructions. The prototypical I-type instruction looks like: add $rt, $rs, immed In this case, $rt is the destination register, and $rs is the only source register. It is unusual that $rd is not used, and that $rd does not appear in bit positions B25-21 for both R-type and I-type instructions. Presumably, the designers of the MIPS ISA had their reasons for not making the destination register at a particular location for R-type and I-type. The semantics of the addi instruction are; R[t] = R[s] + (IR15)16 IR15-0 where IR refers to the instruction register, the register where the current instruction is stored. (IR15)16 means that bit B15 of the instruction register (which is the sign bit of the immediate value) is repeated 16 times. This is then followed by IR15-0, which is the 16 bits of the immediate value. Basically, the semantics says to sign-extend the immediate value to 32 bits, add it (using signed addition) to register R[s], and store the result in register $rt. Jump Type (J-Type) J-type is short for "jump type".  This group consists of the two direct jump instructions (j and jal). These instructions require a memory address to specify their operand. J-type instructions use opcodes 00001x. The prototypical I-type instruction looks like: j target The semantics of the j instruction (j means jump) are: PC <- PC31-28 IR25-0 00 where PC is the program counter, which stores the current address of the instruction being executed. You update the PC by using the upper 4 bits of the program counter, followed by the 26 bits of the target (which is the lower 26 bits of the instruction register), followed by two 0's, which creates a 32 bit address.  PREPARED BY : SITI ROSNIEZA EILISA BINTI JAMAL (B031410230) INSTRUCTION TYPE APPLICATION When MIPS instructions are classified according to coding format, they fall into four categories: R-type, I-type, J-type, and coprocessor. The coprocessor instructions are not considered here. The classification below refines the classification according to coding format, taking into account the way that the various instruction fields are used in the instruction. The details of the execution activities and the required control signal values depend almost entirely on the instruction type in this classification. Non-Jump R-Type Immediate Arithmetic and Logic Branch Load Store Non-Register Jump Register Jump Non-Jump R-Type Non-jump R-type instructions include all R-type instructions except jr and jalr. This includes all of the   integer arithmetic and bitwise operations, along with the non-branching compare instructions such as slt, sgt, and seq. They use the R coding format. The opcode bits are all 0. 31 26 25 21 20 16 15 11 10 6 5 0 op rs rt rd sa fn PC update There is no update beyond the normal increment. Source operand fetch The two source operands are rs and rt. ALU operation The ALU operation is determined by the function field. Memory access There is no memory access for data. Register write The result from the ALU is written to rd. Immediate Operand Most immediate operand instructions perform arithmetic or logical operations using one operand that is coded into the instruction. The immediate operand group also includes the comparison instructions slti and sltiu and the lui instruction. Immediate operand instructions use the I coding format. 31 26 25 21 20 16 15 0 op rs rt imm PC update There is no update beyond the normal increment. Source operand fetch The two source operands are rs and the immediate field. For all instructions except sltiu the immediate field is sign extended. For sltiu the immediate field is zero extended. This instruction is not considered in Patterson and Hennessey. ALU operation The ALU operation is determined by the opcode. Memory access There is no memory access for data. Register write The result from the ALU is written to rt. Branch Branch instructions conditionally branch to an address whose distance is coded into the instruction. Branch instructions use the I coding format. 31 26 25 21 20 16 15 0 op rs rt imm PC update If the branch condition is true (see ALU operation), PC ← PC + 4 + (sign-extended immediate field)<<2. Source operand fetch The two source operands are rs and rt. ALU operation The source operands are subtracted for comparison. Memory access There is no memory access for data. Register write There is no register write. Load Load instructions move data from memory into a register. The address for the load is the sum of a register specified in the instruction and a constant value that is coded into the instruction. Load instructions use the I coding format. 31 26 25 21 20 16 15 0 op rs rt imm PC update There is no update beyond the normal increment. Source operand fetch The two source operands are rs and the sign extended immediate field. ALU operation The two source operands are added to get the memory address. Memory access A memory read control signal is sent to memory. The result from the ALU is sent to memory as the address. Register write The data from memory is written to rt. Store Store instructions move data from a register into memory. The address for the store is the sum of a register specified in the instruction and a constant value that is coded into the instruction. Store instructions use the I coding format. 31 26 25 21 20 16 15 0 op rs rt imm PC update There is no update beyond the normal increment. Source operand fetch The two source operands are rs and the sign extended immediate field. The rt register is also fetched. ALU operation The two source operands are added to get the memory address. Memory access A memory write control signal is sent to memory. The result from the ALU is sent to memory as the address. The contents of rt are sent to memory as the write data. Register write There is no register write. Non-Register Jump The only non-register jump instructions are j and jal. Non-register jump instructions use the J coding format. 31 26 25 0 op target PC update jr and jalr: PC ← target address The target address is the concatenation of the high order 4 bits of PC + 4, the target field of the instruction, and two 0 bits. Source operand fetch There is no source operand fetch. ALU operation There is no ALU operation. Memory access There is no memory access for data. Register write j: There is no register write. jal: $ra ← PC + 4 Register Jump The only register jump instructions are jr and jalr. Register jump instructions use the R coding format. The opcode bits are all 0. 31 26 25 21 20 16 15 11 10 6 5 0 op rs rt rd sa fn PC update jr and jalr: PC ← rs Source operand fetch The only source operand that is used is the rs register. ALU operation There is no ALU operation. Memory access There is no memory access for data. Register write jr: There is no register write. jalr: rd ← PC + 4 Register Jump The only register jump instructions are jr and jalr. Register jump instructions use the R coding format. The opcode bits are all 0. 31 26 25 21 20 16 15 11 10 6 5 0 op rs rt rd sa fn PC update jr and jalr: PC ← rs Source operand fetch The only source operand that is used is the rs register. ALU operation There is no ALU operation. Memory access There is no memory access for data. Register write jr: There is no register write. jalr: rd ← PC + 4 prepared by:NOR FADILA BT MOHD YUNUS B031410253 ADDRESSING MODES           MIPS only has a small number of ways that is  computer addresses in memory. It can be address of an instruction (for branch and jump instructions)   or it can be an address of data (for load and store instruction). 1.     REGISTER ADDRESSING:  used in jr register instruction 2.     PC-RELATIVE ADDRESSING: used in beq and bne instructions 3.     Pseudo-direct addressing: used in j instruction 4.     Base addressing : used in lw and sw instructions REGISTER ADDRESSING §  SIMPLEST ADDRESSING MODE §  BOTH OPERANDS ARE IN A REGISTER  REGISTER DIRECT ADDRESSING:                              §  MOV A, R4 §  At a time registers can take value from R0,R1 to R7,   there are 32 such registers §  There are 4 registers bank named 0,1,2,3 §  Each bank has 8 register banks from R0 to R7 §  Only one register can be selected §  Bits are designated from PSW.0 to PSW.7 §  Register banks are selected using PSW.3 and PSW.4 §  These two bits are known as register bank select bits as   they use to select register bank REGISTER INDIRECT ADDRESSING: Eg: add a,[b] Register b contains an address The contents of this address are added to the accumulator Int x = 2; b = &x; a += *b; REGISTER INDIRECT  WITH  DISPLACEMENT ADDRESSING: Eg: add a,[b+10] Register b contains a number The desired memory address is 10 plus the contents of b The contents of this address are added to the accumulator byte x[20];  /*x is at addr 10*/ b = 5; a += x[b]; IMMEDIATE ADDRESSING §  THE OPERAND IS A CONSTANT WITHIN    THE ENCODED INSTRUCTION §  INSTRUCTIONS WILL BE EXECUTED FASTER    BECAUSE IT DOES NOT INVOLVE MEMORY ACCESS §  JUMP INSTRUCTION FORMAT ALSO FALLS    UNDER IMMEDIATE ADDRESSING                                                       MOV A, #6AH §  Opcode for MOV A,# data is 74H §  Opcode is saved in program memory at 0202 address §  Data 6AH is saved in program memory 0203 §  When opcode 74H is read, the next step taken    would be transfer whatever data the next program    memory address §  This instruction is 2 bytes and is executed in one cycle §  After execution, program counter will add 2 and move    to 0204 of program memory  http://www.massey.ac.nz/~mjjohnso/notes/59233/lect16.html http://www.circuitstoday.com/8051-addressing-modes           PREPARED BY:WAN NORAQILAH BINTI A.RAZAK(B031410306)             Base Addressing Base addressing is also known as indirect addressing,where a register act as a pointer to an operand located at the memory location whose address is in the register. The register is called base that may point to a structure or some other collection of data and immediate value is loaded at a constant offset from the beginning of the structure.The offset specifies how far the location of the operand data from the memory location pointed by the base. The address of the operand is the sum of the offset value and the base value (rs).However,the size of operand is limited to 16 bits because each MIPS instruction fits into a word. The offset value is a signed number which is represented in a two's complement format.Therefore,offset value can also be a negative value. Let's consider the following instruction. lw $rt, offset($rs) where $rs and $rt are any two registers. The offset is stored in 16 bits 2C. Thus, lw and sw are I-type instructions. The address computed is: addr <- R[s] + sign-ext32( offset ) $rs is the base register, which is where the name base addressing comes from. The offset is the 16 bit immediate value from the instruction. Unlike branch instructions, we don't add a 00 to the end of the immediate value, even though we can only load and store are word-aligned addresses. The reason is because there are other load/store instructions that load/store halfwords and bytes, and it makes sense to compute the addresses the same way, regardless of what you're loading. So what happens an address is computed that's not word aligned? An address exception occurs.  http://www.cs.umd.edu/class/sum2003/cmsc311/Notes/Mips/addr.html              Prepared By:Masturah bt mohammad liza , B031410271 PC-RELATIVE ADDRESSING PC-Relative Addressing also known as Program Counter Addressing is a data or instruction memory location is specified as an offset relative to the incremented PC. PC-relative addressing is usually used in conditional branches. PC refers to special purpose register, Program Counter that stores the address of next instruction to be fetched. In PC-relative addressing, the offset value can be an immediate value or an interpreted label value, The effective address is the sum of the Program Counter and offset value in the instruction. The effective address determines the branch target. PC-relative addressing implements position-independent codes. Only a small offset is adequate for shorter loops. Branch instructions can only move 32768 above or below the program counter because the offset is a 16-bit two's complement number. Another word of saying to explain this: The operand address = PC + an offset Implements position-independent codes. A small offset is adequate for short loops. Example: beqz $t0, strEnd where; $t0 = rs            100 = offset Thus; if ($t1 == 0) goto PC + 4 (4*2) In this instruction, beqz is a conditional instruction that branches to label in the code if the content of $t0 is equal to zero. If the current address for branch instruction in execution is 0x4000000C, the effective address will be 40000018.                                                      ADDRESS      INSTRUCTION                                                         40000008 = beq $5, $5, 1                                                        4000000C = beq $0, $5, label                                                         40000010 = addi $5, $5, 1                                                         40000014 = addi, $5, $5, 1                                                         40000018 = label addi $5, $5, 1                                                        4000001C = addi $5, $5, 1                                                         40000020 = etc... Binary code to beq $0,$5, label is 0x10050002, which mans 2 instructions from the next instruction.                                                                   PC =  0x4000000C                                                               PC+4 =   0x40000010                                                          Add 4*2 =   0x00000008                                                         Eff. Add. =   0x40000018 PC-relative addressing occurs in branch instructions, such as beq and bne. These instructions are I-type instructions, with the following format. http://menningwuwu.blogspot.com/2012/12/topic-3-subtopic-4-pc-relative.html http://classes.soe.ucsc.edu/cmpe110/Spring11/lectures/05_MIPS_addressing.pdf PSEUDO-DIRECT ADDRESSING Pseudo-direct Addressing is the memory address which (mostly) embedded in the instructions. Specially used for J-type instructions, j and jal. Effective address is calculate by taking the upper 4 bits of the PC, concatenated to the 26 bits immediate value, and the lower 2 bits are 00. The new effective address will always be word-alidned and we can never have a target address of a jump instruction with 2 bits. * Word-aligned means that an address(unless you use one of the special instructions for loading or storing bytes) must be a multiple of 4. * An address that isn't multiple of 4 can lead to undesirable results. http://allyouneedtoknowaboutcomputer.blogspot.com/2012/12/mips-addressing-mode.html http://oskmadesimple.blogspot.com/2012/12/pseudo-direct-addressing.html http://menningwuwu.blogspot.com/2012/12/topic-3-subtopic-5-jj.html PREPARED BY: SITI NORHAYATI BINTI MASHUDI                               B031410259